98 research outputs found

    Transformation of Conventional Houses to Smart Homes by Adopting Demand Response Program in Smart Grid

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    In an ever-growing state of electricity demand due to population growth as well as modernization of societies, it has compelled us to look for many options to cope with the situations. However, for a balanced electrical power demand and supply, it is necessary to respond requirement at any time without any interruption with the strategy of demand response programs (DRP) to the users. In order to promote smart usage of electrical power, smart grid networks are gradually transforming conventional grids in many places. As a part of smart grid, conventional houses may be transformed to smart house by simply implementing some intelligent controller with interfaces like smart plugs to the conventional electrical appliances. This chapter elaborates a new strategy of home energy management system (HEMS) in a smart grid environment to transform any ordinary premises to smart house to be energy efficient by simply rescheduling operation time

    Close‐Spaced Sublimation (CSS): A Low‐Cost, High‐Yield Deposition System for Cadmium Telluride (CdTe) Thin Film Solar Cells

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    Semiconductors are the key materials in many of our modern day devices, such as sensors, integrated circuits, energy harvesting devices, optoelectronics and so on. However, apart from two known elemental semiconductors that are silicon and germanium, we have been using many of the synthesized ones since the microelectronic revolution known as invention of transistor. Numerous compound semiconductors since then have been synthesized, grown, deposited or simply fabricated by numerous processes in the scientific community. To avoid associated chemical disposals or keep safe from toxic or combustible gas usages in any semiconductor fabrication facilities, many researchers choose physical vapor deposition as the simplest method. One of such processes is called Close-Spaced Sublimation (CSS), which is a kind of thermal evaporation by nature. This chapter would give a comprehensive outline on CSS as one of the most advantageous semiconductor deposition processes for many compound semiconductors having relatively low evaporation temperature. Cadmium telluride (CdTe) is one of the examples utilized for solar cell absorber materials since the early 1980s using CSS technique. Therefore, growth of CdTe thin films by CSS and its utilization in thin film solar cells will be discussed to comprehend the ultimate benefits of the close-spaced sublimation (CSS) process

    Thickness Dependence of The Surface Roughness of Micro Contact Deposited By Dc Magnetron Sputtering Technique

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    Integrated circuits are tested in final step of IC packaging to verify that required electrical connections are working properly. At present, Pogo Pins are used as electrical connection between IC lead and load board. Pogo pins caused different problems including indentation marks, blur marks, tilting, spring malfunction, high maintenance cost and etc. The present miniaturization trends towards higher performance, smaller and lighter product have resulted in an increasing demand for smaller pitch size and increase the issues of testing process with pogo pins. Pogo pins induced reliability problems when dealing with fine-pitch (< 0.5 mm) packages. New electrical conductive cell was designed in previous works. It was based on microstructures instead of pogo pins and consists of three different parts including polymer, metallic micro contactors and liquid metal. New Model was designed for QFP packages with 0.5 mm pitch size using simulation in previous years. Novel test socket mechanical design and analysis were successfully done by previous study. New models with new materials in different shapes were designed and the best one was achieved

    UWB Technology for WSN Applications

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    Prospects Of Molybdenum Thin Film For Solar Cell Application From AFM Analysis

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    Molybdenum (Mo) was grown on soda lime glass by the radio frequency (RF) magnetron sputtering deposition method to characterize the prospect feature to be used as solar cell back contact. 10 samples were sputtered with different suitable parameter by varying RF target power, argon gas pressure and growth temperature. Then all the samples were analyzed by atomic force microscopy (AFM) to determine their features and specification. The results include molybdenum thin film characteristics of roughness, grain size and root mean square (RMS) is obtained. From these characterization results the paramount parameter condition is obtained which at 200 °C, 6.6 mTorr and 75 Watt. These optimized results can be used in future work for fabricating of molybdenum as back contact layer for solar cell application. In conclusion, this study has obtained the optimized parameter in term of growth temperature, argon (Ar) gas pressure and radio frequency (RF) power for molybdenum growth on thin films that compatible and can be integrated not only for solar cell application but with wide variety of MEMS/NEMS devices

    Characterization of transparent conducting carbon nanotube thin films prepared via different methods

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    The fabrication and characterization of transparent conductors based on single walled carbon nanotube (SWCNT) thin films were carried out in controlled environment and its performance compared. Here, we demonstrate the fabrication of thin, transparent, optically homogeneous, electrically conducting films of metallic enriched single-walled carbon nanotubes via three different deposition techniques namely dip coating, vacuum filtration and Langmuir Blodgett. Optical characterization showed that the maximum transmittance, TM, in Vis region is ~ 96.3% and minimum surface roughness, Ra ~ 4.87 nm achieved via Langmuir-Blodgett technique. I-V characteristics shows minimum sheet resistance, Rs ~ 3.62 × 103 Ω/sq and maximum conductivity, σ ~ 27.65 Ω-1cm-1 for vacuum filtration technique. It is shown that SWCNT deposition technique significantly affects the optical and electrical characteristics of resulting thin films. Langmuir Blodgett method produced film with the lowest surface roughness of Ra ~ 4.87 nm and uniform conductivity of σ ~ 0.025 Ω-1cm-1, whereas vacuum filtration method produced film with the highest surface roughness of Ra ~ 12.83 nm and non-uniform conductivity, σ, ranging from ~ 0.199 to ~0.017 Ω-1cm-1 depending on the film dimensions

    Deposition of Micro Contact Based Probe Cell for IC Testing by Dc Magnetron Sputtering Technique

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    This study presents the deposition of micro contact probe cell for IC testing deposited by dc sputtering technique on a glass substrate. Micro contact with thickness of 2800-7000 nm were deposited from Copper target at sputtering power of 125 W in argon ambient at a room temperature on a base layer of copper using mask. Then, the micro contacts were investigated by using profilometer. All the obtained results show the potential viability of the novel test fixture and thus solve the limitatio

    Zero skew clock routing for fast clock tree generation

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    A Zero Skew Clock Routing Methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion, and lastly, routing the connection from original clock source to each newly inserted clock buffers with zero skew. A few Perl scripts and a new Visual Basic based routing tool have been developed to support the methodology implementation. The routing algorithm used in this tool is based on the Exact Zero Skew Routing Algorithm. The methodology has been tested using a real design database and resulting in a significant improvement in the through put time required to complete the clock tree generation. This improvement is attributed to the ability to generate clock tree on much smaller portions of clock nets that supports of speeding up the clock tree generation process in IC design

    Analysis of absorber and buffer layer band gap grading on CIGS thin film solar cell performance using SCAPS

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    A numerical simulation and analysis was performed to investigate the effect of absorber and buffer layer band gap grading and on a Copper-Indium-Gallium-Diselenide (CIGS) solar cell. The software used is the Solar Cell Capacitance Simulator (SCAPS). The absorber and buffer layer energy band structures' effect on the cell's output parameters such as open circuit voltage, short circuit current density, fill factor and efficiency were extensively simulated. Two structures of the energy band gap were simulated and studied for each of the absorber and buffer layer. The simulation was done on the uniform structure in which the energy band gap is constant throughout the layer. It was then continued on the cell with graded band structure, where the energy band gap of the material is varied throughout the layer. It was found that the cell with graded band structure in absorber and buffer layer had demonstrated higher efficiency and better performance in comparison with the cell with uniform band gap structure

    Fast clock tree generation using exact zero skew clock routing algorithm

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    A Zero Skew clock routing methodology has been developed to help design team speed up their clock tree generation process. The methodology works by breaking up the clock net into smaller partitions, then inserting clock buffers to drive each portion and lastly, routing the connection from original clock source to each newly inserted clock buffers with zero skew. A few Perl scripts and a new visual basic based routing tool have been developed to support the methodology implementation. The routing algorithm used in this tool is based on the Exact Zero Skew Routing Algorithm. The methodology has been tested using a real design database and resulting in a significant improvement in the through put time required to complete the clock tree generation. This improvement is attributed to the ability to generate clock tree on much smaller portions of clock nets that supports of speeding up the clock tree generation process in IC design
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